VHDL語法格式

1、VHDL語法格式上篇 基礎(chǔ)元素目錄： 數(shù)據(jù)類型 數(shù)據(jù)對象 運算符 語句 基本程序結(jié)構(gòu) 電路描述方式數(shù)據(jù)類型 預(yù)定義類型 bit bit_victor integer std_logic std_logic_victor 自定義類型 枚舉類型 type 新數(shù)據(jù)類型 is (元素1, 元素2, .) 例 定義 type state_type is (s1, s2, s3. s4);- 定義一個新類型state_type 引用 signal state : state_type;- 定義一個信號state，類型為state_type 數(shù)組類型 type 數(shù)組 is array (范圍) of 數(shù)據(jù)類

2、型; 例 定義 type byte is array (7 downto 0) of bit;- 定義一個8bit的數(shù)組 type word is array (31 downto 0) of bit;- 定義一個32bit的數(shù)組數(shù)據(jù)對象 端口 聲明端口 : in | out 數(shù)據(jù)類型; - 端口在特性上等同于信號，但賦值在entity的port中賦值端口 <= 表達(dá)式; 信號 聲明signal 信號 : 數(shù)據(jù)類型;賦值信號 <= 表達(dá)式; 變量 聲明varable 變量 : 數(shù)據(jù)類型;賦值變量 := 表達(dá)式; 常數(shù) 聲明常數(shù) : 數(shù)據(jù)類型 := 數(shù)值;運算符 算術(shù)運算 +, -,

3、 * 并置運算 & 關(guān)系運算 =, /=, <, <=, >, >= 邏輯運算 and, or, not, nand, nor, xor, xnor語句 并行語句 信號賦值語句 簡單信號賦值語句 信號 <= 表達(dá)式; 選擇信號賦值語句 with 選擇表達(dá)式 select 信號 <= 表達(dá)式1 when 選擇值1, 表達(dá)式2 when 選擇值2, . 表達(dá)式n when others; 條件信號賦值語句 信號 <= 表達(dá)式1 when 條件關(guān)系式1 else 表達(dá)式2 when 條件關(guān)系式2 else . 表達(dá)式n when 條件n else 表

4、達(dá)式; 過程調(diào)用語句 過程 (實參); 函數(shù)調(diào)用語句 信號 <= 函數(shù) (實參); 元件例化語句 元件聲明 component 元件實體 - 將一個實體聲明為元件 port (端口聲明); end component; 元件引用 按位置引用 標(biāo)號 : 元件實體 port map (連接端口1, 連接端口2, .); 按名稱引用 標(biāo)號 : 元件實體 port map (元件端口1 >= 連接端口1, 元件端口2 >= 連接端口2, .); 生成語句 格式 1 標(biāo)號: for 循環(huán)變量 in 取值范圍 generate 聲明語句, begin 并行語句, end generate

5、 標(biāo)號; 取值范圍: 表達(dá)式 to 表達(dá)式; - 遞增方式，如1 to 5 表達(dá)式 downto 表達(dá)式 ; - 遞減方式，如5 downto 1 格式 2 標(biāo)號: if 條件關(guān)系式 generate 聲明語句; begin 并行語句, end generate 標(biāo)號 , 塊語句 塊標(biāo)號: block (保護條件) 接口聲明; 類屬聲明; begin 并行語句; - 被保護的變量前需加上保留字guarded end block 塊標(biāo)號; 帶保護的塊語句舉例: entity latch is port( d, clk : in bit; q, qb : out bit ); end latch;

6、 achetectire latch_guard of latch is begin b1 : block(clk = ¢1¢) begin q <= guarded d after 5 ns; qb <= guarded not(d) after 7 ns; end block b1; end latch_guard 進程語句 標(biāo)號: process (敏感信號) 聲明語句; -常量，變量，信號 begin 順序語句; end process 標(biāo)號:;順序語句 賦值語句 - 在進程中 信號 <= 表達(dá)式; 變量 := 表達(dá)式; 流程控制語句 if語句 格

7、式 1: if 條件關(guān)系式 then 順序語句; end if; 格式 2: if 條件關(guān)系式 then 順序語句; else 順序語句; end if; 格式 3: if 條件關(guān)系式1 then 順序語句; elsif 條件關(guān)系式2 then 順序語句; . else 順序語句; end if; case 語句 - case 語句中，條件值有3種形式：值，值1 | 值2 |.| 值n，值 TO 值 - 最后一行的順序語句若為null,則有意引入鎖存器 case 條件表達(dá)式 is when 條件值 => 順序語句; . when others => 順序語句; end case;

8、for_loop 語句 標(biāo)號: for 循環(huán)變量 in 值 to 值 loop; 順序語句; end loop 標(biāo)號;時鐘邊沿描述 上升沿 時鐘¢event and時鐘 = ¢1¢ | rising_edge (時鐘) 下降沿 時鐘¢event and時鐘 =¢0¢ | falling_edge (時鐘)程序基本結(jié)構(gòu)- 主程序與元件程序在同一文件work1.vhd中，library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std

9、_logic_arith.all;- 主程序entity 實體名 is -實體名必須與文件名相同 port (端口聲明; );end entity work1;architecture struc of work1 is 聲明語句; -常量，變量，信號，元件，函數(shù)等begin 并行語句;end architecture struc;電路描述方式 行為描述方式 以用狀態(tài)機描述電路為典型 數(shù)據(jù)流 ( 寄存器 ) 描述方式 即用邏輯表達(dá)式描述電路 結(jié)構(gòu)描述方式 以用元件復(fù)用的方式描述電路為典型VHDL語法格式下篇 復(fù)合元素和狀態(tài)機目錄元件 - 1 單文件元件 2 多文件元件函數(shù) - 3 單文件函數(shù)

10、4 多文件函數(shù)過程 - 5 單文件過程 6 多文件過程moorl 狀態(tài)機 - 7 二進程moorl狀態(tài)機 8 三進程moorl狀態(tài)機meaky 狀態(tài)機 - 9 二進程mealy狀態(tài)機 10 三進程mealy狀態(tài)機狀態(tài)機實例 - 11 交通燈之一 12 交通燈之二附錄 - 13 狀態(tài)轉(zhuǎn)移圖 14 用戶庫的格式和用法單文件元件- 主程序與元件程序在同一文件work1.vhd中，library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;- 主程序entity work1 is port ( r,s,t,u : i

11、n std_logic; v : out std_logic );end entity work1;architecture struc of work1 is component ym - 將實體ym聲明為元件 port ( a,b : in std_logic; c : out std_logic ); end component ym; component hm - 將實體hm聲明為元件 port ( a,b : in std_logic; c : out std_logic ); end component hm; signal temp1,temp2 : std_logic;begi

12、n u1 : ym port map ( r, s, temp1 ); - 元件例化 u2 : ym port map ( t, u, temp2 ); u3 : hm port map ( temp1, temp2, v );end architecture struc;- ym元件實體定義程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ym is port ( a,b : in std_logic; c : out std_logic );end entity ym;arch

13、itecture ym1 of ym isbegin c <= a and b;end architecture ym1;- hm元件實體定義程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hm is port ( a,b : in std_logic; c : out std_logic );end entity hm;architecture hm1 of hm isbegin c <= a or b;end architecture hm1;多文件元件- 主程序

14、文件和定義元件的程序文件都要添加到工程中- 主程序文件zhu_map.vhd，不需要聲明用戶庫文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity zhu_map is port ( r,s,t,u : in std_logic; v : out std_logic );end entity zhu_map;architecture niu of zhu_map is component ym port ( a,b : in std_logic; c : out std_logic )

15、; end component ym; component hm port ( a,b : in std_logic; c : out std_logic ); end component hm; signal temp1,temp2 : std_logic;begin u1 : ym port map ( r, s, temp1 ); - 元件例化 u2 : ym port map ( t, u, temp2 ); u3 : hm port map ( temp1, temp2, v );end architecture niu;- 定義元件實體的程序文件- ym元件實體定義程序librar

16、y ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ym is port ( a,b : in std_logic; c : out std_logic );end entity ym;architecture ym1 of ym isbegin c <= a and b;end architecture ym1;- hm元件實體定義程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity

17、 hm is port ( a,b : in std_logic; c : out std_logic );end entity hm;architecture hm1 of hm isbegin c <= a or b;end architecture hm1;單文件函數(shù)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity func is port ( din1,din2 : in std_logic_vector( 0 to 3 ); dout : out std_logic_vec

18、tor( 0 to 3 ) );end entity;architecture a of func is- 定義函數(shù) function ls_xj ( d1, d2 : in std_logic_vector( 0 to 3 ) ) return std_logic_vector is variable temp : std_logic_vector( 0 to 3 ); begin temp := d1 + d2; return temp; end function;- 定義函數(shù)結(jié)束begin dout <= ls_xj ( din1, din2 ); -調(diào)用函數(shù)end archite

19、cture;多文件函數(shù)- 主程序文件和定義函數(shù)的程序文件都要添加到工程中- 主程序文件zhu_func.vhd，必須聲明用戶庫文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;use work.use_func.all; - use_func.vhd作為用戶庫entity zhu_func is port ( din1,din2 : in std_logic_vector( 0 to 3 ); dout : out std_logic_vector( 0 to 3 ) );end;architect

20、ure niu of zhu_func isbegin dout <= ls_xj ( din1, din2 ); - 調(diào)用函數(shù)end;- 定義函數(shù)的文件fu_func.vhdlibrary ieee;use ieee.std_logic_1164.all;package use_func is - 聲明 function ls_xj ( d1, d2: in std_logic_vector( 0 to 3 ) ) return std_logic_vector;end use_func;package body use_func is - 程序體 function ls_xj ( d

21、1, d2 : in std_logic_vector( 0 to 3 ) ) return std_logic_vector is variable temp : std_logic_vector( 0 to 3 ); begin temp := d1 and d2; return temp; end function;end use_func;單文件過程library ieee;use ieee.std_logic_1164.all;entity call_proce is port ( d1 : in integer range 0 to 31; d2 : in integer rang

22、e 0 to 31; fout : out integer range 0 to 31 ); end;architecture a of call_proce is- 過程定義 procedure jfq ( din1, din2 : in integer range 0 to 31;dout : out integer range 0 to 31 ) is begin dout := din1 + din2; end;- 過程定義結(jié)束begin process ( d1, d2 ) variable fo : integer range 0 to 31; begin jfq ( d1, d2

23、, fo ); - 調(diào)用過程 fout <= fo; end process;end;多文件過程- 主程序文件和定義過程的程序文件都要添加到工程中- 主程序文件zhu_proc.vhd，必須聲明用戶庫文件library ieee;use ieee.std_logic_1164.all;use work.use_proc.all; - use_proc.vhd作為用戶庫entity zhu_proc is port ( d1, d2 : in integer range 0 to 31; fout : out integer range 0 to 31 ); end;architectur

24、e niu of zhu_proc isbegin process ( d1, d2 ) variable fo : integer range 0 to 31; begin jfq ( d1, d2, fo ); - 調(diào)用過程 fout <= fo; end process;end;- 定義過程的文件fu_proc.vhdlibrary ieee;use ieee.std_logic_1164.all;package use_proc is - 聲明 procedure jfq ( din1 : in integer range 0 to 31;din2 : in integer ra

25、nge 0 to 31;dout : out integer range 0 to 31 );end use_proc;package body use_proc is - 程序體 procedure jfq ( din1, din2 : in integer range 0 to 31;dout : out integer range 0 to 31 ) is begin dout := din1 + din2; end jfq;end use_proc;二進程moorl狀態(tài)機library ieee;use ieee.std_logic_1164.all;entity moorl_1 is

26、port ( reset : in std_logic; clock : in std_logic; din : in std_logic; dout : out std_logic_vector ( 2 downto 0 ) );end entity;architecture statemachine of moorl_1 is type state_type is ( s0, s1, s2, s3 ); signal state : state_type;begin process( reset, clock ) - 變換狀態(tài) begin if reset = '1' th

27、en state <= s0; elsif rising_edge( clock ) then case state is when s0 => if din = '1' then state <= s1; end if; when s1 => if din = '1' then state <= s2; end if; when s2 => if din = '1' then state <= s3; end if; when s3 => if din = '1' then sta

28、te <= s0; else state <= s1; end if; end case; end if; end process; process( state ) - 輸出 begin case state is when s0 => dout <= "001" when s1 => dout <= "011" when s2 => dout <= "101" when s3 => dout <= "111" end case; end process

29、;end;三進程moorl狀態(tài)機library ieee;use ieee.std_logic_1164.all;entity moorl_2 isport ( reset : in std_logic; clock : in std_logic; din : in std_logic; dout : out std_logic_vector( 2 downto 0 ) );end entity;architecture statemachine of moorl_2 is type state_type is ( s0, s1, s2, s3 ); signal presentstate :

30、 state_type; signal nextstate : state_type;begin process ( reset, clock ) - 更新當(dāng)前狀態(tài) begin if reset = '1' then presentstate <= s0; elsif rising_edge ( clock ) then presentstate <= nextstate; end if; end process; process ( presentstate, din ) - 生成下一個狀態(tài) begin case presentstate is when s0 =

31、> if din = '1' then nextstate <= s1; else nextstate <= s0; end if; -dout <= "001" when s1 => if din = '1' then nextstate <= s2; else nextstate <= s1; end if; -dout <= "011" when s2 => if din = '1' then nextstate <= s3; else ne

32、xtstate <= s2; end if; -dout <= "101" when s3 => if din = '1' then nextstate <= s0; else nextstate <= s1; -dout <= "111" end if; end case; end process; process ( presentstate ) - 輸出 begin case presentstate is when s0 => dout <= "001" when

33、 s1 => dout <= "011" when s2 => dout <= "101" when s3 => dout <= "111" end case; end process;end;二進程mealy狀態(tài)機library ieee;use ieee.std_logic_1164.all;entity mealy_1 isport ( reset : in std_logic; clock : in std_logic; din : in std_logic; dout : out std_

34、logic_vector ( 2 downto 0 ) );end entity;architecture statemachine of mealy_1 is type state_type is ( s0, s1, s2, s3 ); signal state : state_type;begin process ( reset, clock ) - 變換狀態(tài) begin if reset = '1' then state <= s0; elsif rising_edge ( clock ) then case state is when s0 => if di

35、n = '1' then state <= s1; end if; when s1 => if din = '1' then state <= s2; end if; when s2 => if din = '1' then state <= s3; end if; when s3 => if din = '1' then state <= s0; else state <= s1; end if; end case; end if; end process; process ( s

36、tate, din ) - 輸出 begin case state is when s0 => if din='0' then dout <="000" else dout <="001" end if; when s1 => if din='0' then dout <="010" else dout <="011" end if; when s2 => if din='0' then dout <="100

37、" else dout <="101" end if; when s3 => if din='0' then dout <="110" else dout <="111" end if; end case; end process;end architecture;三進程mealy狀態(tài)機library ieee;use ieee.std_logic_1164.all;entity mealy_2 isport ( reset : in std_logic; clock : in std

38、_logic; din : in std_logic; dout : out std_logic_vector( 2 downto 0 ) );end entity;architecture statemachine of mealy_2 is type state_type is ( s0, s1, s2, s3 ); signal presentstate : state_type; signal nextstate : state_type;begin process ( reset, clock ) - 更新當(dāng)前狀態(tài) begin if reset = '1' then

39、presentstate <= s0; elsif rising_edge ( clock ) then presentstate <= nextstate; end if; end process; process ( presentstate, din ) - 生成次態(tài) begin case presentstate is when s0 => if din ='1' then nextstate <= s1; else nextstate <= s0; end if; when s1 => if din ='1' the

40、n nextstate <= s2; else nextstate <= s1; end if; when s2 => if din ='1' then nextstate <= s3; else nextstate <= s2; end if; when s3 => if din = '1' then nextstate <= s0; else nextstate <= s1; end if; end case; end process; process ( presentstate, din ) - 輸出 be

41、gin case presentstate is when s0 => if din = '0' then dout <= "000" else dout <= "001" end if; when s1 => if din = '0' then dout <= "010" else dout <= "011" end if; when s2 => if din = '0' then dout <= "100&